发明名称 |
SIGNALVERARBEITUNGSSYSTEM |
摘要 |
A signal processing system contains a source apparatus coupled to a destination apparatus via a bus operable according to a time-slot allocation protocol. The source apparatus is arranged for supplying a sequence of packets, each having a time-stamp via the bus to the destination apparatus. The destination apparatus includes a clock and is arranged for receiving the packets, for detecting when the time-value of the clock corresponds to the time-stamp in a particular packet, and for thereupon presenting data from that particular packet at an output, operable according to a time-slot allocation protocol. The source apparatus is arranged for supplying a first and a second part of at least one of the packets in different time-slots, the destination apparatus being arranged for presenting data from the first and second part together upon detecting when the time-value of the clock corresponds to the time-stamp in the at least one of the packets. |
申请公布号 |
AT255801(T) |
申请公布日期 |
2003.12.15 |
申请号 |
AT19950921093T |
申请日期 |
1995.06.22 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
BLOKS, RUDOLF, HENRICUS, JOHANNES |
分类号 |
H04J3/24;H04L12/40;H04L12/407;H04L12/417;H04L12/64;H04N7/24;H04N7/26;H04N7/50;H04N7/52;H04N21/41;H04N21/43;H04N21/434;H04N21/4363;H04Q11/04;(IPC1-7):H04Q11/04;H04N7/62 |
主分类号 |
H04J3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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