发明名称 Method to form shallow trench isolations
摘要 A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.
申请公布号 US6649486(B1) 申请公布日期 2003.11.18
申请号 US20000679510 申请日期 2000.10.06
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD. 发明人 BALAKUMAR SUBRAMANIAN;LEE KONG HEAN;ZHOU ZHENG;WANG XIAN BIN
分类号 H01L21/762;(IPC1-7):H01L21/76 主分类号 H01L21/762
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