| 摘要 |
<p>PURPOSE:To quickly reset registers to a pattern where '0' and '1' exist together by fixing the scan clock input terminal of each register to a significant value and using an inverting gate or the like for connection between desired registers in a scan path. CONSTITUTION:A mode switching input terminal 4 is set to the scan mode, and clocks of a scan A clock input terminal 5 and a scan B clock input terminal 6 are set to the turning-on state, and a scan input terminal 2 is fixed to '0'. Then, scan data flows to the scan path so that a value indicated in each register 1 is obtained. Thereafter, the gate delay time is considered to turn off clocks of the scan A clock input terminal 5 and the scan B clock input terminal 6, and thus, the reset operation is terminated, and respective registers 1 are quickly reset to a pattern where '0' and '1' exist together. With respect to the connection order of the scan path constitution in this case, registers to be reset to '0' are connected as a group, and an inverting gate 7 is next connected, and registers to be reset to '1' are finally connected as a group.</p> |
