Clock-controlled flip-flop has 2 parallel hold stages with common input operated in anti-phase by clock signal, multiplexer with 2 inputs connected to hold outputs, output forming flip-flop output

摘要

The flip-flop has two parallel hold stages (L1,L2) with a common input signal (D) and operated in anti-phase by the clock signal (CLK) followed by a multiplexer (MUX) with two inputs (A,B) connected to the hold circuit outputs and one output forming the flip-flop output (Q). The multiplexer is controled by the clock signal. At least one of the hold circuits is a static hold circuit. Independent claims are also included for the following: (a) a method of switching a signal through with a flip-flop (b) and a clock-blocking circuit with an inventive flip-flop.