| 摘要 |
A system for maintaining data flow between buses is provided wherein the bandwidth of a first bus is less than the bandwidth of a second bus. The bandwidth of a bus is based on the clock speed of the bus and the bit width of the bus. The system includes a first bus having a first clock rate and a first bus-width, a second bus having a second clock rate and a second bus-width, and control logic. The control logic receives data from the first bus and transfers the data to the second bus. The control logic may comprise a set of storage devices selectively coupled to the first bus and the set of storage devices may be addressable memory. The control logic may further include a first bus control logic for writing data to the set of storage devices and a second bus control logic for reading data to from the set of storage devices.
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