发明名称 Method and mechanism for synchronizing a slave's timer to a master's timer
摘要 A circuit for synchronizing an internal time signal to an external time signal includes a first timer, a second timer, and a comparator. The first timer repetitively increments and outputs a first time signal. The second timer repetitively outputs a second time signal. The comparator drives an active comparator signal if the first time signal is greater than the second time signal, or otherwise an inactive signal. The first timer saves the second time signal as the first time signal in response to a control signal derived from the inactive comparator signal and repetitively increments and outputs the first time signal. Alternatively, the first timer freezes, i.e., preventing the repetitive incrementing, of the first time signal in response to a control signal derived from the active comparator signal. The second timer repetitively increments and outputs the second time signal in response to a control signal derived from the active comparator signal. When the first time signal becomes less than or equal to the second time signal, the first timer unfreezes the first time signal in response to a control signal derived from the inactive comparator signal.</PTEXT>
申请公布号 US6633989(B1) 申请公布日期 2003.10.14
申请号 US19990452272 申请日期 1999.11.30
申请人 LSI LOGIC CORPORATION 发明人 HOLLINS JACK B.
分类号 H04J3/06;(IPC1-7):G06F1/12;G06F1/04 主分类号 H04J3/06
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