| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a small-sized and inexpensive burst data receiver which maintains high clock accuracy and a function of absorbing the jitters of a selected clock of a digital PLL (phase-locked loop). <P>SOLUTION: A VCXO 11 is provided as a clock source of a multi-phase clock 201 of a digital PLL 16. Then, an analog PLL 15 is provided to divide the frequency of a clock 202 including jitters selected by the clock selection circuit 4 from the multi-phase clock of the digital PLL 16 by a frequency dividing circuit 9-3 and employ the resultant frequency division clock 402 as the control voltage 400 of the VCXO 11 via an LPF (low-pass filter) 12. Then, the difference 501 between the received OH phase of burst data and its expected reception phase is detected by an OH detection timing generation circuit 7, and the duty of the frequency dividing clock 402 of the frequency dividing circuit 9-3 is controlled according to the difference by a duty adjustment circuit 13. Thus, the operation source clock of the digital PLL 16 is made common with the operation source clock of the analog PLL 15. <P>COPYRIGHT: (C)2004,JPO |
