| 摘要 |
The invention provides improved methods and systems for generation of square roots of vector and administrative operands. The methods utilize bit-manipulation operations to halve intermediate values, generated by a processor reciprocal square root operation, during a multistep process square root determination. Such methods can also multiply an original operand (whose square root is being determined) with such an intermediate value, e.g., or a halved or other value thereon. The invention also provides methods and apparatus for determination of square roots square roots of large groups of numbers by interleaving vector and administrative instructions to take advantage of necessary delays in the vector processing pipeline architecture to speed overall processing. |
