发明名称 |
Memory cell with a vertical transistor and fabrication method thereof |
摘要 |
A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.
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申请公布号 |
US2005167721(A1) |
申请公布日期 |
2005.08.04 |
申请号 |
US20040845909 |
申请日期 |
2004.05.14 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
LIN SHIAN-JYH;HSU YU-SHENG |
分类号 |
H01L21/334;H01L21/76;H01L21/8242;H01L27/108;H01L29/732;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/334 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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