发明名称 Discrete-time convolution cycle reduction with programmable digital signal processor
摘要 A programming algorithm reduces from theta (2N2) to theta (N2) the number of multiply-and-accumulate (MAC) instructions required to perform a discrete-time convolution on a programmable digital signal processor. Through the use of a single repeat instruction along with a single repeat count register, the algorithm dynamically changes the number of times the multiply-accumulate instruction is repeated depending upon the current term being convolved. The avoids performing the multiply-accumulate when one term is zero. The nature of the discrete-time convolution calculation and the flexibility of a re-programmable single repeat count register offers permits this. Additional instructions are required for data pointer alignment. The trade-off between reduced multiply-accumulate operations and the overhead required to achieve it is examined.
申请公布号 US7580965(B2) 申请公布日期 2009.08.25
申请号 US20020256588 申请日期 2002.09.27
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 JAHNKE STEVEN R.
分类号 G06F17/15;G06F17/10 主分类号 G06F17/15
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