Method and apparatus for enhancing input/output error analysis in hardware sub-systems

摘要

A method, apparatus, and computer instructions for processing errors in a hierarchical hardware sub-system in the data processing system in which the hierarchical hardware sub-system includes a host processor bridge having a mapping registers section and a control and status registers section. In response to detecting an error freezing the mapping registers section in the host bridge, a component within the hierarchical hardware sub-system connected to the host bridge is identified to form a selected component. An address is written to a register within the control and status registers section of the host bridge in which the address is to an error register in the component. Data is read in response to a result from the address written in the register being placed in the control and status registers portion of the host bridge.