| 摘要 |
PROBLEM TO BE SOLVED: To reduce a jitter contained in the output signal of a pulse wave generator even when the frequency of a basic clock oscillator cannot be made sufficiently large for the output signal. SOLUTION: A clock distributor 12 respectively distributes four clocks CLK0, CLK90, CLK180 and CLK270 of different phases of 0°, 90°, 180°and 270°from the basic clock to pulse output circuits 13, 14, 15 and 16. As common data, frequency control data C and pulse frequency setting data D are respectively inputted to the pulse output circuits 13 to 16 and 0, D/4, D/2 and 3D/4 are individually inputted as initial values. The outputs of the pulse output circuits 13 to 16 are passed through an AND gate 17 to become the clock input of a one-bit holding circuit 19 and passed through an OR gate 18 to become the reset input of the one-bit holding circuit 19. COPYRIGHT: (C)2003,JPO |
