发明名称
摘要 In a test circuit for a semiconductor integrated circuit, a counter circuit generates a control signal based on a comparison result between test results and expected data from a comparison circuit and outputs the control signal to a tri state buffer. The tri state buffer operates based on the received control signal. The counter circuit outputs the generated control signal to the tri state buffer in order that the tri state buffer outputs the test result to the outside of the test circuit only when the test results are not equal to the expected data.
申请公布号 KR100396096(B1) 申请公布日期 2003.08.27
申请号 KR20000007335 申请日期 2000.02.16
申请人 发明人
分类号 G01R31/26;G01R31/28;G01R31/3193;G06F11/22;G11C29/40;H01L21/822;H01L27/04 主分类号 G01R31/26
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