发明名称 SEMICONDUCTOR MEMORY AND ITS FABRICATING METHOD
摘要 PROBLEM TO BE SOLVED: To increase the capacitive coupling ratio between a floating gate and a control gate. SOLUTION: The capacitive coupling ratio is increased by a virtual ground semiconductor memory comprising a floating gate provided on a semiconductor substrate through a gate insulation film, a control gate of polysilicon layer provided to cover the upper surface of the floating gate and a part of the sidewall in the direction of channel width starting from the upper surface of the floating gate, diffusion bit lines provided on the opposite sides of the floating gate in the direction of channel width, and a silicide layer formed while being self-aligned on the control gate and the diffusion bit lines. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003229499(A) 申请公布日期 2003.08.15
申请号 JP20020028410 申请日期 2002.02.05
申请人 SHARP CORP 发明人 KANEKO SEIJI
分类号 H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 主分类号 H01L21/8247
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