发明名称 Semiconductor memory device including page latch circuit
摘要 A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.
申请公布号 US2003151955(A1) 申请公布日期 2003.08.14
申请号 US20020270673 申请日期 2002.10.16
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NODA JUNICHIRO;IKEHASHI TAMIO;IMAMIYA KENICHI
分类号 G11C29/02;(IPC1-7):G11C5/00 主分类号 G11C29/02
代理机构 代理人
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