发明名称 TEST FACILITATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a test facilitating circuit capable of reducing required cost for test of a semiconductor device. SOLUTION: A TIC 13 having a simple PG which is mounted on a mixed loading memory device is constituted of a command analysis part 21 which analyzes a 3 bits command received from a tester, outputs an analysis result to a memory core, and controls action of the memory core; and an address counter 22 which counts addresses and outputs the count to the memory core in accordance with a 2 bits counter control instruction received from the tester. Consequently, a circuit scale for testing of the memory core can be miniaturized and also the number of pins for testing of memory can be reduced, and an inexpensive tester can be used and the cost required for testing of the memory core can be reduced. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003223798(A) 申请公布日期 2003.08.08
申请号 JP20020017390 申请日期 2002.01.25
申请人 MITSUBISHI ELECTRIC CORP 发明人 TANIZAKI TETSUSHI
分类号 G01R31/28;G01R31/3183;G01R31/3185;G11C29/02;G11C29/12;G11C29/14;G11C29/20;(IPC1-7):G11C29/00;G01R31/318 主分类号 G01R31/28
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