| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay locked loop (DLL) circuit which can lock a phase more speedily. <P>SOLUTION: This DLL circuit is equipped with a delay circuit 20 between a clock buffer 5 and an output buffer 10 so as to put the input clock CLK inputted to the clock buffer 5 and the output clock OCLK outputted from the output buffer 10 in phase with each other. When an apparatus equipped with such a DLL circuit is powered ON, an internal oscillation circuit 80 generates clocks of a number corresponding to the number of delay units needed to put the input clock CLK and output clock OCLK in phase with each other. Then a counter 90 counts the number of clocks and a shift register 70 controls a delay circuit 20 according to the count value. <P>COPYRIGHT: (C)2003,JPO |
