| 摘要 |
PURPOSE: An 1/2 power voltage generation circuit and a semiconductor memory device by using the same are provided to implement a stable operation although the level of the power voltage becomes low. CONSTITUTION: An 1/2 power voltage generation circuit includes a first to a third PMOS transistors(P1-P3) and a first to a third NMOS transistors(N1-N3). In the 1/2 power voltage generation circuit, the gate of the first PMOS transistor(P1) is connected to the source applied thereto the power voltage(VCC) and the drain thereof to the node(C). The drain and gate of the first NMOS transistor(N1) is connected to the drain of the first PMOS transistor(P1) and the source thereof to the node(A). The source of the second PMOS transistor(P2) is connected to the node(A) and the gate and drain thereof to the node(D). The drain of the second NMOS transistor(N2) is connected to the node(B), the gate thereof to the node(B) and the source thereof to the ground voltage. The drain of the third NMOS transistor(N3) is connected to the power voltage(VCC), the gate thereof to the node(C) and the source thereof to the node(B). And, the source of the third PMOS transistor(P3) is connected to the node(B), the gate thereof to the node(D) and the drain thereof to the ground. The 1.2 power voltage generation circuit further includes a first resistor(R1) connected between the source and the drain of the first PMOS transistor(P1) and a second resistor(R2) connected between the drain and the source of the second NMOS transistor(N2).
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