发明名称 Signal amplitude limiting circuit and filter circuit
摘要 A signal amplitude limiting circuit includes a differential circuit, a feed back circuit and a voltage supply circuit. The differential circuit has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The feedback circuit is connected to the first differential circuit. The feedback circuit compares voltages at the positive and negative output terminals with a reference voltage and outputs a comparison signal in response to the comparison. The voltage supply circuit is connected to the differential circuit and the feedback circuit. The first voltage supply circuit provides a current to the differential circuit in response to the comparison signal.
申请公布号 US2003132793(A1) 申请公布日期 2003.07.17
申请号 US20030340599 申请日期 2003.01.13
申请人 YOSHIDA YOSHIKAZU;HORIKAWA AKIRA 发明人 YOSHIDA YOSHIKAZU;HORIKAWA AKIRA
分类号 H03F3/45;(IPC1-7):H03L5/00 主分类号 H03F3/45
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