发明名称 |
Interconnect methodology employing a low dielectric constant etch stop layer |
摘要 |
The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 Å and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.
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申请公布号 |
US6593632(B1) |
申请公布日期 |
2003.07.15 |
申请号 |
US19990375500 |
申请日期 |
1999.08.17 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
AVANZINO STEVEN C.;NGO MINH VAN;HUI ANGELA T.;JIANG CHUN;PARTOVI HAMID |
分类号 |
H01L21/314;H01L21/768;H01L23/535;(IPC1-7):H01L29/76;H01L29/94 |
主分类号 |
H01L21/314 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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