发明名称 Zero clock skew computer module
摘要 The length of the phase lock feedback path of the phase lock loop chip (PLL chip) is adjusted so that the timing of clock pulses at computer chips is measured relative to the arrival time of a clock pulse at the computer board clock pin. This adjustment of the length of the phase lock loop accounts for the length of the trace from the computer board clock pin to the PLL clock input pin. This adjustment of the length of the phase lock loop removes uncertainty between vendors in the arrival time of clock pulses at the computer chips, relative to arrival time of clock pulses at the computer board clock pin. A system designer then has control of the arrival time of a pulse at a computer chip clock pin by adjustment of the arrival time of the clock pulse at the computer board clock pin, and no variation is introduced between vendors who adopt the invention in their design of computer boards.
申请公布号 US6591372(B1) 申请公布日期 2003.07.08
申请号 US19990392599 申请日期 1999.09.09
申请人 COMPAQ COMPUTER CORPORATION 发明人 NERL JOHN
分类号 G06F1/10;(IPC1-7):G06F1/10 主分类号 G06F1/10
代理机构 代理人
主权项
地址