| 发明名称 |
Memory controller and data processing system |
| 摘要 |
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
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| 申请公布号 |
US6587934(B2) |
申请公布日期 |
2003.07.01 |
| 申请号 |
US20010931860 |
申请日期 |
2001.08.20 |
| 申请人 |
HITACHI, LTD. |
发明人 |
MIURA SEIJI;AYUKAWA KAZUSHIGE |
| 分类号 |
G11C7/00;G06F12/02;G11C11/401;G11C11/407;(IPC1-7):G06F12/00 |
主分类号 |
G11C7/00 |
| 代理机构 |
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