| 摘要 |
PURPOSE: A method for fabricating a metal interconnection of a semiconductor device is provided to improve a filling characteristic by selectively filling a metal material only in a via hole and a trench through an electroless plating method. CONSTITUTION: The via hole and the trench are formed in an interlayer dielectric on a lower metal interconnection(22). A barrier metal layer and a catalyst metal layer are sequentially formed on the resultant structure. The catalyst metal layer is selectively eliminated to be left only in the via hole and the trench. The metal material is filled in the via hole and the trench.
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