发明名称 |
Datenprozessor zum gleichzeitigen Dataladen und Durchführung einer multiplizier-addier Operation |
摘要 |
A data processor comprises an instruction decode unit (119) for receiving operation codes from an instruction memory (103).
A second decoder (114) of the instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives 2 data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes 2 data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116). |
申请公布号 |
DE69627807(D1) |
申请公布日期 |
2003.06.05 |
申请号 |
DE1996627807 |
申请日期 |
1996.12.05 |
申请人 |
MITSUBISHI DENKI K.K., TOKIO/TOKYO |
发明人 |
MATSUO, MASAHITO;YOSHIDA, TOYOHIKO |
分类号 |
G06F9/30;G06F9/302;G06F9/32;G06F9/34;G06F9/355;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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