发明名称 |
System and method for improving multi-bit error protection in computer memory systems |
摘要 |
A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.
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申请公布号 |
US6574746(B1) |
申请公布日期 |
2003.06.03 |
申请号 |
US19990347117 |
申请日期 |
1999.07.02 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
WONG TAYUNG;SINGHAL ASHOK;FANG CLEMENT;CARRILLO JOHN;KO HAN Y. |
分类号 |
G06F11/10;G06F12/16;G11C29/42;(IPC1-7):G06F11/08 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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