发明名称 PLL system for CRT monitor
摘要 A PLL system includes a phase comparator, charge pump, LPF, VCO, 1/N frequency divider, CRT drive circuit, and arithmetic unit. The charge pump outputs a charge pump signal in accordance with the phase error signal output from the phase comparator. The current capacity of the charge pump is controlled to keep a PLL loop gain constant by compensation for a variation in PLL loop gain due to a change in a frequency division ratio 1/N in the frequency divider.
申请公布号 US6573798(B2) 申请公布日期 2003.06.03
申请号 US20010901726 申请日期 2001.07.11
申请人 NEC ELECTRONICS CORPORATION 发明人 UTO YOSHIYUKI
分类号 H04N5/06;G09G1/04;G09G5/18;H03L7/08;H03L7/089;H03L7/093;H03L7/10;H03L7/18;H04N3/16;H04N3/27;(IPC1-7):H03L7/00 主分类号 H04N5/06
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