| 摘要 |
PURPOSE: A storage circuit with an odd-even check unit array is provided to test a real cell array and a parity cell array properly. CONSTITUTION: According to a memory circuit, a real cell array(RCA) stores data, and a parity or ECC generating circuit generates a parity bit or an ECC from data of the real cell array. A parity or ECC cell array stores the parity bit or ECC. A refresh control circuit generates an internal refresh request signal at a predetermined cycle and sequentially refreshes the real cell array in accordance with a refresh address, and, when an internal refresh request and a read request coincide, prioritizes a refresh operation for the real cell array(RCA). A data recovery section, in accordance with the parity bit or ECC read out from the parity or ECC cell array, recovers data read out from the real cell array(RCA) for which the refresh operation has been prioritized. An output circuit outputs data from the real cell array(RCA) via the data recovery section. And a test control circuit(38), in the first test mode, prohibits a refresh operation for the real cell array(RCA) to thereby output data read out from the real cell array(RCA), and, in the second test mode, controls the output circuit so as to output data read out from the parity or ECC cell array.
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