发明名称 |
SEMICONDUCTOR MEMORY AND ITS TEST METHOD |
摘要 |
PROBLEM TO BE SOLVED: To improve quality of a test by providing a semiconductor memory in which logical data can be made coincide with physical data without reducing efficiency of redundancy relieving. SOLUTION: This device is provided with a data inversion control circuit 17 for redundancy performing inversion control of input/output data (I/O) in accordance with activating redundant word lines (SWL(0), SWL(1)), and a data inversion circuit 18 taking exclusive OR of an output signal of the data inversion control circuit for redundancy and an external input data signal and exclusive OR of an output signal of the data inversion control circuit for redundancy and an external output data signal.
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申请公布号 |
JP2003157695(A) |
申请公布日期 |
2003.05.30 |
申请号 |
JP20010354435 |
申请日期 |
2001.11.20 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
OTSUKA HIDEFUMI;YAMAZAKI HIROYUKI;ORIGASA KENICHI |
分类号 |
G01R31/28;G11C11/401;G11C29/00;G11C29/04;G11C29/56;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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