| 摘要 |
PROBLEM TO BE SOLVED: To further improve access speed in a semiconductor memory adopting a late select system to which a lower order bit selecting way of a memory cell array out of read-out addresses is inputted late. SOLUTION: This device is provided with a plurality of data selectors 31, 32 selecting respectively either of a plurality of read-out data read from a plurality of ways and write data held in a WD register 41 for the late select system, and a way selector 35 selecting way data specified by a way selecting signal SAS inputted at read-cycle out of a plurality of outputs of these data selector 31, 32 and passing through them to an output side, further provided with a logic circuit 30 generating a signal by which a data selector of a way side specified by a write address SA of the WL register 13 selects a held write data side when the read-out address SA inputted at read-cycle coincides with a corresponding bit of a write address held in the WA register 13.
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