发明名称 |
Designing of logic circuit for testability |
摘要 |
The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.
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申请公布号 |
US2003097347(A1) |
申请公布日期 |
2003.05.22 |
申请号 |
US20020190158 |
申请日期 |
2002.07.05 |
申请人 |
DATE HIROSHI;HOSOKAWA TOSHINORI;MURAOKA MICHIAKI |
发明人 |
DATE HIROSHI;HOSOKAWA TOSHINORI;MURAOKA MICHIAKI |
分类号 |
G01R31/28;G01R31/317;G06F17/50;(IPC1-7):G06G7/00;G06F17/00;G06N5/02 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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