发明名称 |
Performance verification/analysis tool for full-chip designs |
摘要 |
A method and apparatus may be provided for providing performance verification/analysis of a full-chip design. This may include performing an analysis on a first block of the full-chip design. Data (such as a waveform output from a pin of the block) may be captured while performing the analysis. This captured data may be utilized when performing an analysis of the full-chip design. Features of an interconnect between the first block and a second block may be determined using the captured data.
|
申请公布号 |
US6564357(B2) |
申请公布日期 |
2003.05.13 |
申请号 |
US20010820876 |
申请日期 |
2001.03.30 |
申请人 |
INTEL CORPORATION |
发明人 |
KAY RONY;KURUPATI SREENATH |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|