| 摘要 |
828,122. Circuits employing bi-stable magnetic elements. OLIVETTI & CIE S.p.A. ING. C. Jan. 23, 1958 [Feb. 2, 1957], No. 2319/58. Class 40 (9). [Also in Group XIX] In a matrix memory comprising a multidimentional array of bi-stable storage elements located by the intersections of co-ordinate lines associated with driving means, the parallel co-ordinate lines of at least one dimension are associated in pairs, each pair being so coupled to common driving means that a driving pulse of one polarity is adapted to drive the elements of one line toward a given state whereas a driving pulse of reversed polarity is adapted to drive the elements of the other line toward the same state, the elements of the unselected line remaining unaffected. As shown, a magnetic core matrix 54 has column wires y individually coupled, and row wires, such as x, x<1> coupled in pairs to driving transformers arranged in similar submatrices 61 and 62. The row address is set up on binary registers 68, 73 associated with diode gating decoders 67, 77 (only one of the gates being shown). The selecting output of decoder 67 (say on line 33) is negative, thus cutting-off inverter tube 36 and rendering cathode follower 66 conductive to produce a positive potential on the corresponding horizontal selecting line 65 of transformer submatrix 62. The selecting output of decoder 77 is positive, thus priming a pair of gate tubes 69, 70 coupled to a pair of vertical transformer selecting lines 153a, 153b ; the tubes such as 69, 70 are normally cut-off by positive potentials at their cathodes due to conduction of cathode followers 81, 83. During a magnetic core read/write cycle, negative pulses are applied successively via terminals 84, 85 to diode gates 86, 89 controlled by the outputs of a further element 74 of register 73. According to the state of this element, these negative pulses are transmitted to 81, 83 or 83, 81 respectively which are thus cut-off, the associated primed tubes 69, 70 then being rendered conductive to lower the potential on lines 153a, 153b or 153b, 153a successively. When, e.g. line 153a is negative, current flows to this line from line 65 via a centre tap on the primary of the selected transformer (59) and diode 19, thus causing current flow in one direction in secondary 58; similarly, a reduced potential on line 153b causes current flow in the other direction. Each secondary in the rowselecting submatrix 62 is connected to a pair of the row wires (x, x<1>) which are joined at 149, whereby current in the two wires will always flow in opposite directions in relation to the cores. The column address is similarly set up on registers 46, 47 which through similar circuits selects a transformer, such as 151, in submatrix 61, whereby successive read/write current pulses of opposite directions are induced in secondary 150 connected to a single column wire y, these pulses tending to drive the associated cores first to the " 0 " state then back to the " 1 " state. To select and read, e.g. core 71 at the intersection of wires x, y, output 75 of element 74 is made negative to select gates 86, 88, whereby the read and write pulses from 84, 85 cut-off cathode followers 81, 83, respectively. The current pulses thus induced through the transformer secondary 58 in row wire x are of the same sense in relation to the cores as the pulses induced through secondary 150 in column wire y ; since the pulses induced in wire x<1> are of opposite sense, core 72 will not be affected. If, however, element 74 is reversed, the pulses induced in 58 and 150 will be such as to select core 72 and to have no effect on core 71. If a " 1 " is read from a selected core, a pulse is induced in read winding 101 and applied via rectifier 102, amplifier 103, strobe-pulse controlled gate 104 and pulse shaper 106, e.g. to other parts of a computer in which the memory is included. During the write period, a control pulse from 115, fed through gate 111 or 112, according to whether terminal 113 or 114 (connected to the outputs of element 74) is energized, to pulse generator 109 or 110 and inhibit winding 107 or 108, inhibits writing in the selected core, these windings being coupled to the rows of cores associated with wires such as x and wires such as x<1> respectively. If, however, a " 1 " signal is obtained either from shaper 106 or from input terminal 118, gates 111 and 112 are inhibited and the writing of a " 1 " by the coincident pulses from the submatrices 61, 62 is not inhibited. Different wiring arrangements for the row wires and inhibit windings are described in a matrix memory comprising parallel planes arranged in pairs on opposite sides of insulating boards. The driving transformers may be replaced by bidirectional or unidirectional transistors. |
