| 摘要 |
PROBLEM TO BE SOLVED: To reduce the cell area of an SRAM device, while suppressing increase of amplification delay in its bit line. SOLUTION: In a CMOS SRAM device having its memory cell comprising six transistors, the channel widths (gate widths) of drive and access transistors MN1, MN3 which constitute one of the two sets of CMOS inverters are made nearly equal to each other and are made larger than the channel widths of drive and access transistors MN0, MN2 which constitute the other of the two sets of CMOS inverters. Also, between the basic circuits comprising the two sets of CMOS inverters, the off-leakage currents of the inverters are made unsymmetrical to cut down the leakage current of the SRAM device which is generated in its waiting time, while securing the large cell-current of one of the two sets of CMOS inverters. |
