发明名称 |
Detection of errors in dynamic circuits |
摘要 |
Logic is connected to the outputs of a dynamic logic gate to detect illegal or invalid states. The output of this detection logic sets a state catcher. The output of the state catcher is readable by scan logic so that the occurrence or non-occurrence of the invalid state may be read by test hardware.
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申请公布号 |
US2003042933(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
US20010947585 |
申请日期 |
2001.09.05 |
申请人 |
HILL J. MICHAEL;LACHMAN JONATHAN E.;PARKER CLINTON H. |
发明人 |
HILL J. MICHAEL;LACHMAN JONATHAN E.;PARKER CLINTON H. |
分类号 |
G01R31/3185;(IPC1-7):H03K19/096 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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