发明名称 |
Output buffer circuit for reducing variation of slew rate due to variation of PVT and load capacitance of output terminal, and semiconductor device including the same |
摘要 |
An output buffer circuit for reducing a variation of the slew rate due to a variation of process, voltage and temperature (PVT) and the load capacitance of an output terminal, and semiconductor device including the same, include a first slew rate control circuit for pulling down the voltage of a pull-up signal in multiple stages in response to a first control signal, and a second slew rate control circuit for pulling up the voltage of a pull-down signal in multiple stages in response to a second control signal. A pull-up driver is provided for pulling up an output terminal in response to the pull-up signal, and a pull-down driver is provided for pulling down the output terminal in response to the pull-down signal. The first and second slew rate control circuits are controlled by bias voltages that are provided by a phase locked loop circuit and compensate for changes in PVT.
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申请公布号 |
US2003042953(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
US20020229976 |
申请日期 |
2002.08.28 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SHIN SOON-KYUN |
分类号 |
G11C11/417;G06F3/00;G11C11/40;H03K5/00;H03K5/13;H03K17/687;H03K19/003;H03K19/0175;H03K19/0948;H03L7/099;(IPC1-7):H03K5/12 |
主分类号 |
G11C11/417 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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