发明名称 |
PIPELINE ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP DIGITAL CALIBRATION |
摘要 |
A multi-stage pipeline analog-to-digital converter employs an internal digital domain error detection and calibration algorithm to eliminate accumulated digital truncation errors to thereby improve its accuracy and linearity.
|
申请公布号 |
WO03013002(A1) |
申请公布日期 |
2003.02.13 |
申请号 |
WO2002US23934 |
申请日期 |
2002.07.26 |
申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
HISANO, SHINICHI |
分类号 |
H03M1/10;H03M1/16;(IPC1-7):H03M1/10 |
主分类号 |
H03M1/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|