REGISTER AND SIGNAL GENERATING METHOD

摘要

PURPOSE: To provide a register capable of coping with a wide frequency range and without depending on the number of mounted devices. CONSTITUTION: A value of an external delay replica 50 is fixed and set by assuming the maximum value of the number of devices to be coped with. Setting of the realistic maximum and minimum values to an internal delay replica 403 is possible by dividing a desired frequency range into a plurality of sub- frequency ranges and using delay quantity of an output buffer and the internal delay replica 403 by switching them by every individual sub-frequency range. Selection of the delay quantity in the internal delay replica 403 can be performed by a selection pin 404. Thus, sufficient setup time and hold time are secured to an internal clock signal intCLK generated by DLL(Delay Locked Loop) regarding a latch operation inside the register without depending high/low of frequency and the number of mounted devices if the frequency is within the desired range and unless the permitted number of devices is exceeded.