| 摘要 |
An alignment technique can be used to align a semiconductor wafer during wafer testing. During a gross alignment process, a bump pattern on the wafer surface is located. Based on a known relative location relationship between the bump pattern and a fiducial on the wafer surface, the fiducial can be located. The wafer can then be initially aligned. During a fine alignment process, the bump pattern technique can again be used and additional alignment performed. Blurring can be used so that features other than bumps become less discernable.
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