A semiconductor storage having memory cells each composed of a selection MIS transistor (Qt), a write MIS transistor (Qw), and a sense MIS transistor (Qs). The semiconductor storage is of a gain−cell type that amplifies the stored information by means of the sense MIS transistor (Qs). The write MIS transistor (Qw) is a vertical transistor fabricated over the sense MIS transistor (Qs), and a selection MIS transistor (Qt) is fabricated on the side face of the write MIS transistor (Qw) in a self−alignment manner. Consequently, the area of each memory cell is small.
