| 摘要 |
A semiconductor device in which the number of steps intrinsic to a memory cell is reduced to as small a value as possible to realize reduction in cell size and invulnerability against software error. A gate oxide film 306 and a capacitance insulating film 310 are formed by one and the same oxide film forming step, while a gate electrode 305 and a charge holding electrode 309 are formed by one and the same electrode forming step. A capacitance electrode connecting local interconnection 311 and a bit line connection local connection 312 are formed by the same interconnection forming step whilst active areas 303 neighboring in the word line direction are arranged with an offset of one gate electrode 305. An area of the isolation film 302 between extending word lines is arrayed adjacent to the Z-Z' direction of the capacitance forming diffusion layer 307 of the active area 303. A trench 304 can be arranged in an isolation oxide film 302 between throughout-extending word lines in a direction 90° offset from the long side direction of the active area 303. There is no pattern of a charge holding electrode 309 such that the trench 304 can be arranged proximate to both side gate electrodes 305 at a separation of approximately one-fourth the minium separation of the gate electrodes.
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