Low-consumption power-on reset circuit for semiconductor memories

摘要

A power-on reset circuit connected to a supply line feeding a supply voltage, the circuit including an output terminal supplying a power-on reset signal; a divider connected between the supply line (36) and ground and having an intermediate node supplying a division voltage correlated to the supply voltage; an inverter having an input connected to the intermediate node and an output connected to the output terminal and supplying a reset logic signal; and a deactivation branch coupled to the supply line and the intermediate node. The deactivation branch preventing switching of the power-on reset signal on the output terminal when the supply voltage is higher than a deactivation voltage.