| 摘要 |
An apparatus and a method for accurately controlling the phase of a sampling clock signal in an LCD system, wherein the sampling clock is generated by a phase lock loop and delayed in response to a phase delay quantity generated by a controller. The controller continuously generates a first phase delay quantity until a horizontal line width of a digital image signal is equal to a desired width, stores a first total phase delay quantity corresponding to how many times the first phase delay quantity was generated, continuously generates a second phase delay quantity until the current horizontal line width is greater than the desired width, stores a second total phase delay quantity corresponding to how many times the second phase delay quantity was generated, and controls the phase delay of the sampling clock in response to an optimum phase delay quantity which is an average of the first and second phase delay quantities.
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