| 摘要 |
PURPOSE: A method for fabricating a MOSFET is provided to reduce gate resistance and a gate delay time by providing a method for forming gate salicide with wide width. CONSTITUTION: A gate electrode(10) including a gate oxide layer is formed on a semiconductor substrate. The first insulating layer spacer(22) is formed on a sidewall of the gate electrode(10). At this time, an upper portion of the sidewall of the gate electrode(10) is exposed. An epi-silicon layer(32) is formed on the exposed silicon substrate and the exposed gate electrode. The second insulating layer spacer(42) is formed on the first insulating layer spacer(22). The first and the second salicide layers(52,54) are formed on the exposed silicon substrate and the exposed gate electrode.
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