发明名称 FAIL BIT MEMORY DEVICE OF IC TESTER
摘要 PROBLEM TO BE SOLVED: To store fail data to a DRAM. SOLUTION: This device has a plurality of memory blocks 2-1 to 2-n for storing fail data FD in an interleave method. Each of the plurality of memory blocks comprises memory means 3-1 to 3-n each having a DRAM which is occasionally rewritable as a memory element for storing fail data, data holding means 4-1 to 4-n each of which fetches the fail data to be written into the memory means and sequentially outputs the fetched fail data, data reading/ writing means 5-1 to 5-n each of which overwrites the fail data output from the data holding means on the fail data in the memory means corresponding to the fail data, and control means 6-1 to 6-n each of which allows the memory means to execute a refreshing operation for rewriting the fail data overwritten in the memory means and allows the data holding means to hold the fail data fetched during the refreshing operation until the refreshing operation is completed.
申请公布号 JP2003004812(A) 申请公布日期 2003.01.08
申请号 JP20010187024 申请日期 2001.06.20
申请人 HITACHI ELECTRONICS ENG CO LTD 发明人 OKA TAKASHI;ONISHI AKIRA;KASHIMA KAZUKI
分类号 G01R31/28;(IPC1-7):G01R31/28 主分类号 G01R31/28
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