A control gate decoder for twin MONOS memory with two bit erase capability

摘要

The present invention is a decoder for control gate lines of a twin MONOS flash memory array. Decoder units connected to each control gate line of the memory are controlled to provide select, override and unselect voltages to perform read, program and erase operations. The decoder units are divided into odd and even addressing where separate voltages can be applied control gates of to adjacent memory cells. Override voltages, which prevent operations of a selected cell from affecting adjacent memory cell storage sites, can be applied to the control gates of immediate neighboring cells of the selected sell. Unselected voltages can be applied to beyond the immediate neighboring cells to further prevent disturb conditions in remote cells. <IMAGE>