发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY HAVING A DECREASED GATE LENGTH AND MANUFACTURING METHOD THEREOF
摘要 An enhanced non-volatile semiconductor memory has a source region and a drain region provided in a semiconductor substrate, an electric charge accumulating portion provided on a channel region between the source and drain regions and a control gate provided on said channel region and at least said source region is provided by introducing an impurity in self-alignment with a side wall provided on a side surface of said control gate, characterized in that an overlap of said drain region with said electric charge accumulating portion is set larger than an overlap of said source region with said electric charge accumulating portion, and an impurity dose quantity of said source region is larger than an impurity dose quantity of said drain region. The drain region may be formed by self alignment manner using a first side wall and the source region may be formed by self alignment manner using a second side wall formed on the first side wall.
申请公布号 US2003001195(A1) 申请公布日期 2003.01.02
申请号 US19990451619 申请日期 1999.11.30
申请人 MORI SEIICHI 发明人 MORI SEIICHI
分类号 G11C16/04;H01L21/265;H01L21/28;H01L21/336;H01L21/8247;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L29/788 主分类号 G11C16/04
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