发明名称 Variable delay element test circuit
摘要 A loop circuit including a variable delay element whose delay time amount can be set arbitrarily is formed, a loop control circuit controls so that the positive/negative logic of input pulse signal to the variable delay element is always constant, the number of output of output pulse signal of the variable delay element is counted, agreement of that count value and a predetermined set value is detected, an agreement detection signal is generated when the agreement is detected, and the transmission of output pulse signal of the variable delay element to the following circuits is controlled based on this agreement detection signal.
申请公布号 US6499334(B1) 申请公布日期 2002.12.31
申请号 US20000667101 申请日期 2000.09.21
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KOBAYASHI NORIFUMI
分类号 G01R31/28;G01R31/30;G01R31/3193;H03K5/13;H03K5/156;(IPC1-7):G01R33/28 主分类号 G01R31/28
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