发明名称 |
Circuit arrangement for the lowering of the threshold voltage of a diode configured transistor |
摘要 |
The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.
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申请公布号 |
US6501673(B2) |
申请公布日期 |
2002.12.31 |
申请号 |
US20010881661 |
申请日期 |
2001.06.13 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
LISI CARLO;BEDARIDA LORENZO;GERACI ANTONINO;DIMA VINCENZO |
分类号 |
G11C16/28;(IPC1-7):G11C16/00 |
主分类号 |
G11C16/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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