发明名称 |
Circuit and method for stress testing a static random access memory (SRAM) device |
摘要 |
A stress test circuit and method for static random access memory ("SRAM") cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.
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申请公布号 |
US6501692(B1) |
申请公布日期 |
2002.12.31 |
申请号 |
US20010953767 |
申请日期 |
2001.09.17 |
申请人 |
CIRRUS LOGIC, INC. |
发明人 |
MELANSON JOHN L.;PANTELAKIS DIMITRIS;JENSEN ROBERT A.;SHENOY VIKRAM |
分类号 |
G11C29/50;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/50 |
代理机构 |
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地址 |
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