| 摘要 |
PURPOSE: A method for manufacturing a CMOS is provided to prevent a gate depletion effect that generates at a conventional dual-polycrystal silicon gate electrode and a Boron diffusion phenomenon. CONSTITUTION: An epitaxial layer is formed on a first and second conductive well. A gate insulation layer and a first metal layer of a second conductivity are sequentially formed on the resultant structure. A second conductive metal gate electrode is formed on the first and second conductive wall by etching selectively the gate insulation layer and the first metal layer. A second conductive source/drain region is formed on the first conductive wall at both sides of the second conductive metal gate electrode. A first conductive source/drain region is formed on the first conductive wall at both sides of the second conductive metal gate electrode. An interlayer dielectric is formed on the semiconductor substrate including the second conductive metal gate electrode. The second conductive metal gate at an upper portion of the second wall is exposed by etching the interlayer dielectric. The second metal gate electrode is removed. The second metal layer of the first conductivity is formed on the resultant structure. The first conductive metal gate electrode at an upper portion of the second conductive wall is formed by etching the second metal layer at an upper portion of the interlayer dielectric.
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